The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jun. 21, 2019
Applicant:

Ansys, Inc., Canonsburg, PA (US);

Inventors:

Norman Chang, Fremont, CA (US);

Hao Zhuang, San Jose, CA (US);

Ganesh Tsavatapalli, Bangalore, IN;

Joao Geada, Chelmsford, MA (US);

Sankar Ramachandran, Bangalore, IN;

Rahul Rajan, Kerala, IN;

Ying-Shiun Li, Pleasanton, CA (US);

Yaowei Jia, San Jose, CA (US);

Mathew Joseph Kaipanatu, Kerala, IN;

Suresh Kumar Mantena, Pradesh, IN;

Assignee:

Ansys, Inc., Canonsburg, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/367 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/367 (2020.01);
Abstract

Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.


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