The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Apr. 17, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Christine Y Ouyang, Hsinchu, TW;

Ziwei Fang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/31 (2006.01); H01L 21/32 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28158 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6681 (2013.01); H01L 29/66553 (2013.01); H01L 29/7854 (2013.01); H01L 21/0206 (2013.01); H01L 21/31127 (2013.01);
Abstract

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess exposing a semiconductor strip and forming an inhibition layer over an interior surface of the spacer element. The method further includes forming a gate dielectric layer in the recess to selectively cover the semiconductor strip. The inhibition layer substantially prevents the gate dielectric layer from being formed on the inhibition layer. In addition, the method includes forming a metal gate electrode over the gate dielectric layer.


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