The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Feb. 28, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Kensuke Ota, Yokohama, JP;

Masumi Saitoh, Yokohama, JP;

Kiwamu Sakuma, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01); H01L 27/11524 (2017.01); H01L 27/11539 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11539 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract

A semiconductor memory device includes a substrate, a plurality of conductive layers, a first semiconductor layer, a memory portion, and a drive circuit which drives the memory cell. The conductive layers are provided in a first region, a second region, and a third region different from the first region and the second region, and a portion positioned in the third region is insulated from a portion positioned in the first region and the second region. The drive circuit is provided in the third region, and includes a second semiconductor layer, and an insulating layer, and one end of the second semiconductor layer is connected to the conductive layers in the second region and the other end of the second semiconductor layer is connected to the substrate.


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