The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Nov. 28, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Allen Ke, Hsinchu, TW;
Yi-Wei Chiu, Kaohsiung, TW;
Hung Jui Chang, Changhua County, TW;
Yu-Wei Kuo, Hsinchu, TW;
Assignee:
Tawiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/74 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76849 (2013.01); H01L 21/4828 (2013.01); H01L 21/743 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 2224/05093 (2013.01);
Abstract
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.