The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Mar. 27, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Reynaldo Corpuz Javier, Plano, TX (US);

Alok Kumar Lohia, Dallas, TX (US);

Andy Quang Tran, Grand Prairie, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2017.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
G06T 7/0008 (2013.01); H01L 23/49503 (2013.01); H01L 23/49555 (2013.01); H01L 23/49568 (2013.01); H01L 24/00 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H05K 3/3421 (2013.01); H05K 2201/10689 (2013.01); H05K 2201/10969 (2013.01);
Abstract

An IC assembly including an exposed pad integrated circuit ('IC') package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit ('IC') package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.


Find Patent Forward Citations

Loading…