The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Jun. 29, 2018
Intel Corporation, Santa Clara, CA (US);
Christopher J. Nelson, Gilbert, AZ (US);
Shelby G. Rollins, Hillsboro, OR (US);
Hiren V. Tilala, Chandler, AZ (US);
Matthew Hendricks, Redwood City, CA (US);
Sundar V. Pathy, Chandler, AZ (US);
Timothy J. Callahan, Hillsboro, OR (US);
Jared Pager, Portland, OR (US);
James Neeb, Gilbert, AZ (US);
Bradly Inman, Hillsboro, OR (US);
Stephen Sturges, Portland, OR (US);
Intel Corportion, Santa Clara, CA (US);
Abstract
Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.