The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
Feb. 20, 2020
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc China Company, Limited, Shanghai, CN;
XiuLi Yang, Shanghai, CN;
Kuan Cheng, Shanghai, CN;
He-Zhou Wan, Shanghai, CN;
Ching-Wei Wu, Caotun Town, TW;
Wenchao Hao, Shanghai, CN;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC CHINA COMPANY, LIMIIED, Shanghai, CN;
Abstract
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.