The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
May. 15, 2020
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Byeong Chan Lee, Pleasanton, CA (US);
Tejinder Singh, San Jose, CA (US);
Bencherki Mebarki, Santa Clara, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H01L 21/308 (2006.01); H01L 21/033 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0217 (2013.01); H01L 21/02266 (2013.01); H01L 21/0337 (2013.01); H01L 21/28568 (2013.01); H01L 21/3083 (2013.01); H01L 21/31051 (2013.01); H01L 21/32133 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract
Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.