The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Mar. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vijay K. Nair, Mesa, AZ (US);

Digvijay Raorane, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/78 (2013.01); H01L 21/82 (2013.01); H01L 23/48 (2013.01); H01L 23/49827 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.


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