Pre-boosting scheme during a program operation in a memory sub-system

Abstract

Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic causes a second positive pre-boosting voltage to be applied to a second plurality of word lines of the data block during the pre-boosting phase, wherein the second plurality of word lines is adjacent to the first plurality of wordlines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive pre-booting voltage has a lower magnitude than the first positive pre-boosting voltage. The control logic further causes the second positive pre-boosting voltage to be ramped down to a ground voltage during the pre-boosting phase prior to the first positive pre-boosting voltage being ramped down to the ground voltage.