Three-dimensional memory devices with backside isolation structures

Abstract

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.