The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Feb. 11, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wan-Yao Wu, Hsinchu, TW;

Chang-Yun Chang, Taipei, TW;

Ming-Chang Wen, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/401 (2013.01);
Abstract

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.


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