The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Dec. 07, 2020
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Hsien Huang, Tainan, TW;

Ching-Cheng Lung, Tainan, TW;

Yu-Tse Kuo, Tainan, TW;

Shu-Ru Wang, Taichung, TW;

Chun-Yen Tseng, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/04 (2006.01); G11C 15/00 (2006.01); H01L 27/02 (2006.01); H01L 27/11 (2006.01); G06F 7/74 (2006.01);
U.S. Cl.
CPC ...
G11C 15/04 (2013.01); H01L 27/0207 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); G06F 7/74 (2013.01); G11C 15/00 (2013.01);
Abstract

A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.


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