The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jun. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Chung-Yen Chou, Hsinchu, TW;

Lee-Chuan Tseng, New Taipei, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Ru-Liang Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00238 (2013.01); B81C 2203/0792 (2013.01);
Abstract

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.


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