The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Sep. 12, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chen Yu Chen, Hsinchu, TW;

Ming Chyi Liu, Hsinchu, TW;

Eugene Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 33/00 (2010.01); H01L 33/62 (2010.01); H01S 5/18 (2021.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/95 (2013.01); H01L 25/0756 (2013.01); H01L 33/005 (2013.01); H01L 33/62 (2013.01); H01S 5/18 (2013.01); H01L 2225/06513 (2013.01);
Abstract

In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.


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