The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Nov. 01, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua M. Rubin, Albany, NY (US);

Kamal K. Sikka, Poughkeepsie, NY (US);

Steven Lorenz Wright, Cortlandt Manor, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01);
Abstract

Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.


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