The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Sep. 02, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Hanno Melzner, Putzbrunn, DE;

Markus Dankerl, Munich, DE;

Peter Irsigler, Obernberg/Inn, AT;

Sebastian Schmidt, Munich, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0696 (2013.01); H01L 29/4236 (2013.01); H01L 29/435 (2013.01);
Abstract

A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.


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