The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jan. 18, 2017
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Kohei Adachi, Tokyo, JP;

Katsutoshi Sugawara, Tokyo, JP;

Yutaka Fukui, Tokyo, JP;

Rina Tanaka, Tokyo, JP;

Kazuya Konishi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/12 (2006.01); H01L 29/10 (2006.01); H02M 1/08 (2006.01); H02M 7/5387 (2007.01); H02P 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/12 (2013.01); H01L 29/78 (2013.01); H01L 29/7813 (2013.01); H02M 1/08 (2013.01); H02M 7/53871 (2013.01); H02P 27/08 (2013.01);
Abstract

A semiconductor device including: a trench gate; a trench-bottom protecting layer of a second conductivity type provided in a semiconductor layer of a first conductivity type while contacting a bottom of trenches; and a depletion suppressing layer of the first conductivity type provided between adjacent trench-bottom protecting layers, wherein the depletion suppressing layer includes an intermediate point that is horizontally equidistant to the adjacent trench-bottom protecting layers and is formed of a size to contact neither the trenches nor the trench-bottom protecting layers, and an impurity concentration of the depletion suppressing layer is set higher than an impurity concentration of the semiconductor layer.


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