The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Dec. 24, 2019
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Nicholas LiCausi, Watervliet, NY (US);

Julien Frougier, Albany, NY (US);

Keith Donegan, Saratoga Springs, NY (US);

Hyung Woo Kim, Watervliet, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 45/00 (2006.01); H01L 23/532 (2006.01); H01L 27/24 (2006.01); H01L 27/22 (2006.01); H01L 27/11587 (2017.01); H01L 27/1159 (2017.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 23/53295 (2013.01); H01L 27/1159 (2013.01); H01L 27/11587 (2013.01); H01L 27/222 (2013.01); H01L 27/24 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/16 (2013.01);
Abstract

One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.


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