The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jun. 05, 2018
Applicant:

Siltronic Ag, Munich, DE;

Inventors:

Stefan Welsch, Polling, DE;

Christof Weber, Burghausen, DE;

Axel Beyer, Burghausen, DE;

Assignee:

SILTRONIC AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); B24B 37/005 (2012.01); B24B 37/04 (2012.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); B24B 37/005 (2013.01); B24B 37/042 (2013.01); H01L 21/02024 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02661 (2013.01); H01L 21/3065 (2013.01); H01L 21/30625 (2013.01);
Abstract

Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.


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