The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2021
Filed:
May. 22, 2020
Applicant:
Xcelsis Corporation, San Jose, CA (US);
Inventors:
Javier A Delacruz, San Jose, CA (US);
Eric Nequist, Saratoga, CA (US);
Jung Ko, San Jose, CA (US);
Kenneth Duong, San Jose, CA (US);
Assignee:
Xcelsis Corporation, San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/12 (2020.01);
Abstract
An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.