The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Mar. 28, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0274 (2013.01); H01L 21/8249 (2013.01); H01L 27/0623 (2013.01);
Abstract
A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.