The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Jun. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shu-Yuan Ku, Hsinchu County, TW;

Chih-Ming Sun, New Taipei, TW;

Chun-Fai Cheng, Tin Shui Wai, HK;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/762 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76232 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/088 (2013.01); H01L 29/4011 (2019.08); H01L 29/785 (2013.01); H01L 21/823437 (2013.01); H01L 29/66795 (2013.01);
Abstract

Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.


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