The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Mar. 13, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Andreas Gerd Ropers, Aachen, DE;

Sylvain Bayon de Noyer, Tokyo, JP;

Alexandru Fiodorov, Aachen, DE;

Filip Constant Thoen, San Jose, CA (US);

Markus Wedler, Aachen, DE;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 11/362 (2013.01);
Abstract

One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.


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