The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Oct. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/3086 (2013.01); H01L 21/823431 (2013.01); H01L 29/66681 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor structure and a method for forming a semiconductor structure are disclosed. A forming method may include: providing a base, including a first region used to form a well region and a second region used to form a drift region, where the first region is adjacent to the second region; and patterning the base, to form a substrate and fins protruding out of the substrate, where the fins include first fins located at a junction of the first region and the second region and second fins located on the second region, where the quantity of the second fins is greater than the quantity of the first fins. In some implementations of the present disclosure, the quantity of the second fins is increased to correspondingly increase the length of a flow path in which a current flows from a drain region to a source region, thereby reducing a voltage drop in the current flow path, and further improving a breakdown voltage of an LDMOS, to improve the device performance of the LDMOS.


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