The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Sep. 27, 2020
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chin-Hung Chen, Tainan, TW;

Chih-Kai Hsu, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Chia-Jung Hsu, Tainan, TW;

Chun-Ya Chiu, Tainan, TW;

Yu-Hsiang Lin, New Taipei, TW;

Po-Wen Su, Kaohsiung, TW;

Chung-Fu Chang, Tainan, TW;

Guang-Yu Lo, New Taipei, TW;

Chun-Tsen Lu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 21/308 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 21/3086 (2013.01); H01L 29/401 (2013.01); H01L 21/28211 (2013.01); H01L 21/31111 (2013.01); H01L 29/511 (2013.01); H01L 29/66674 (2013.01); H01L 29/7801 (2013.01);
Abstract

The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.


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