The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Feb. 05, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Li Hong Xiao, Wuhan, CN;

Bin Hu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 27/06 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); H01L 21/822 (2006.01); H01L 23/31 (2006.01); H01L 27/10 (2006.01); H01L 27/11551 (2017.01); H01L 27/11565 (2017.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 16/0483 (2013.01); H01L 21/8221 (2013.01); H01L 23/3114 (2013.01); H01L 27/101 (2013.01); H01L 27/11551 (2013.01); H01L 27/11565 (2013.01); H01L 27/11578 (2013.01);
Abstract

Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.


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