The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Sep. 30, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Yen-Cheng Liu, Portland, OR (US);
P. Keong Or, Portland, OR (US);
Krishnakanth V. Sistla, Beaverton, OR (US);
Ganapati Srinivasa, Portland, OR (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/20 (2006.01); G06F 15/80 (2006.01); G06F 12/0811 (2016.01); G11C 7/10 (2006.01); G06F 1/3234 (2019.01); G06F 1/3203 (2019.01); G06F 1/3287 (2019.01); G06F 1/324 (2019.01); G06F 1/3206 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/206 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 12/0811 (2013.01); G06F 15/80 (2013.01); G11C 7/1072 (2013.01); G11C 7/1075 (2013.01); G06F 2212/283 (2013.01); Y02D 10/00 (2018.01);
Abstract
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.