The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2021
Filed:
Dec. 20, 2018
Intel Corporation, Santa Clara, CA (US);
Ido Ouziel, Ein Carmel, IL;
Arie Aharon, Haifa, IL;
Dror Caspi, Kiryat Yam, IL;
Baruch Chaikin, D.N. Misagv, IL;
Jacob Doweck, Haifa, IL;
Gideon Gerzon, Zichron Yaakov, IL;
Barry E. Huntley, Hillsboro, OR (US);
Francis X. Mckeen, Portland, OR (US);
Gilbert Neiger, Portland, OR (US);
Carlos V. Rozas, Portland, OR (US);
Ravi L. Sahita, Portland, OR (US);
Vedvyas Shanbhogue, Austin, TX (US);
Assaf Zaltsman, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor includes a processor core. A register of the core is to store: a bit range for a number of address bits of physical memory addresses used for key identifiers (IDs), and a first key ID to identify a boundary between non-restricted key IDs and restricted key IDs of the key identifiers. A memory controller is to: determine, via access to bit range and the first key ID in the register, a key ID range of the restricted key IDs within the physical memory addresses; access a processor state that a first logical processor of the processor core executes in an untrusted domain mode; receive a memory transaction, from the first logical processor, including an address associated with a second key ID; and generate a fault in response to a determination that the second key ID is within a key ID range of the restricted key IDs.