The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Oct. 17, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Chun-Hui Yu, Hsinchu County, TW;

Jeng-Nan Hung, Taichung, TW;

Kuo-Chung Yee, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/473 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/31 (2006.01); H01L 21/50 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 21/50 (2013.01); H01L 23/3135 (2013.01); H01L 23/3185 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 21/308 (2013.01);
Abstract

A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.


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