The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Dec. 17, 2019
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Perrine Batude, Grenoble, FR;

Francois Andrieu, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/02667 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/32053 (2013.01); H01L 21/76254 (2013.01); H01L 21/76895 (2013.01); H01L 21/84 (2013.01); H01L 21/022 (2013.01); H01L 21/0217 (2013.01); H01L 21/02181 (2013.01);
Abstract

A production of a device with superimposed levels of components including in this order providing on a given level Nprovided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N, above said given level N, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.


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