The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Jan. 31, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu, TW;

Ke-Jing Yu, Kaohsiung, TW;

Fu-Hsiang Su, Hsinchu, TW;

Yi-Ju Chen, Tainan, TW;

Jyh-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H01L 21/76832 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01);
Abstract

A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.


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