The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Aug. 31, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Abu Naser Zainuddin, Milpitas, CA (US);

Ohwon Kwon, Pleasanton, CA (US);

Jiahui Yuan, Fremont, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 5/14 (2006.01); G11C 11/4097 (2006.01); G11C 11/4094 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 5/146 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 11/5642 (2013.01);
Abstract

Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.


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