The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2021
Filed:
Aug. 31, 2020
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Annie Lum, San Jose, CA (US);
Derek C. Tao, Fremont, CA (US);
Cheng Hung Lee, Hsinchu, TW;
Chung-Ji Lu, Fongyuan, TW;
Hong-Chen Cheng, Hsinchu, TW;
Vineet Kumar Agrawal, Santa Clara, CA (US);
Keun-Young Kim, Campbell, CA (US);
Pyong Yun Cho, Fremont, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.