The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2021
Filed:
Apr. 18, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/32 (2006.01); H01L 23/535 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H01L 21/28026 (2013.01); H01L 21/28088 (2013.01); H01L 21/31051 (2013.01); H01L 21/32 (2013.01); H01L 23/535 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01); H01L 29/6656 (2013.01);
Abstract
A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.