The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jul. 16, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ding-Kang Shih, New Taipei, TW;

Cheng-Long Chen, Hsin-Chu, TW;

Pang-Yen Tsai, Hsin-Chu Hsian, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/0262 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02636 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/167 (2013.01); H01L 29/45 (2013.01); H01L 29/66636 (2013.01);
Abstract

A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.


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