The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jun. 17, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jin-Aun Ng, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/41791 (2013.01); H01L 29/42372 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a plurality of first nanostructures, a plurality of second nanostructures, two tensile epitaxial structures, two compressive epitaxial structures, and a dielectric layer over the substrate. The method includes forming a gate dielectric layer over the first nanostructures and the second nanostructures. The method includes forming a first work function metal layer over the gate dielectric layer over the first nanostructures. The method includes forming a second work function metal layer over the gate dielectric layer over the second nanostructures. The method includes forming a compressive gate electrode layer over the first work function metal layer using an atomic layer deposition process or a chemical vapor deposition process. The method includes forming a tensile gate electrode layer over the second work function metal layer using a physical vapor deposition process.


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