The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jun. 01, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Katherine Chiang, New Taipei, TW;

Chung-Te Lin, Tainan, TW;

Min Cao, Martinez, CA (US);

Randy Osborne, Beaverton, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01); H01L 43/12 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1659 (2013.01); G11C 11/161 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); H01L 27/226 (2013.01); H01L 27/228 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01);
Abstract

In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.


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