The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Dec. 20, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Fang Chen, Hsinchu, TW;

Jhon Jhy Liaw, Zhudong Township, TW;

Min-Chang Liang, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/53295 (2013.01); H01L 29/41791 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 27/0207 (2013.01);
Abstract

A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.


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