The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Nov. 14, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Rajasekhar Venigalla, Boise, ID (US);

Patrick M. Flynn, Boise, ID (US);

Josiah Jebaraj Johnley Muthuraj, Meridian, ID (US);

Efe Sinan Ege, Boise, ID (US);

Kevin Lee Baker, Boise, ID (US);

Tao Nguyen, Boise, ID (US);

Davis Weymann, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1293 (2013.01); G11C 13/0004 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/1608 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2013/005 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/52 (2013.01); G11C 2213/71 (2013.01); H01L 45/143 (2013.01);
Abstract

Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.


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