The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

May. 31, 2020
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Tzu-Hung Lin, Hsinchu, TW;

Thomas Matthew Gregorich, San Diego, CA (US);

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 23/49838 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 21/563 (2013.01); H01L 23/3192 (2013.01); H01L 24/81 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05011 (2013.01); H01L 2224/0519 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/1308 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.


Find Patent Forward Citations

Loading…