The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Dec. 24, 2019
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Nicholas LiCausi, Watervliet, NY (US);

Julien Frougier, Albany, NY (US);

Keith Donegan, Saratoga Springs, NY (US);

Hyung Woo Kim, Watervliet, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53228 (2013.01); G11C 5/06 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53257 (2013.01);
Abstract

One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.


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