The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Dec. 26, 2018
Applicant:

Sj Semiconductor (Jiangyin) Corporation, Jiangyin, CN;

Inventors:

Yenheng Chen, Jiangyin, CN;

Chentar Wu, Jiangyin, CN;

Chengchung Lin, Jiangyin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 23/15 (2013.01); H01L 23/3128 (2013.01); H01L 23/3192 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/66 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/11 (2013.01);
Abstract

The present application provides a semiconductor packaging structure with an antenna assembly, including: a substrate with through-substrate-via holes; a rewiring layer, located on the substrate; metal bumps, located on and electrically connected to the rewiring layer; a semiconductor chip, located on a surface of the rewiring layer and electrically connected to the rewiring layer; a conductive column, filling in the via hole; a bottom filling layer filling up a gap between the semiconductor chip and the rewiring layer; a polymer layer surrounding the metal bumps and the semiconductor chip; and an antenna assembly, which is electrically connected to one metal bump through the conductive column and the rewiring layer. By using the foregoing solution, the rewiring layer and the metal bumps facilitate proper packaging design.


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