The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Dec. 21, 2018
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Nicolas Posseme, Sassenage, FR;

Cyrille Le Royer, Tullins-Fures, FR;

Yves Morand, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/80 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01); C23C 14/06 (2006.01); C23C 14/48 (2006.01); C23C 16/34 (2006.01); C23C 28/04 (2006.01); H01L 21/02 (2006.01); H01L 21/223 (2006.01); H01L 21/3115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); C23C 14/0652 (2013.01); C23C 14/48 (2013.01); C23C 16/345 (2013.01); C23C 28/04 (2013.01); H01L 21/0217 (2013.01); H01L 21/0234 (2013.01); H01L 21/02118 (2013.01); H01L 21/02271 (2013.01); H01L 21/02321 (2013.01); H01L 21/2236 (2013.01); H01L 21/31155 (2013.01); H01L 21/823807 (2013.01); H01L 29/7843 (2013.01);
Abstract

There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.


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