The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Sep. 12, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yun-Chang Hsu, Hsinchu, TW;

Sheng-Liang Pan, Hsinchu, TW;

Huan-Just Lin, Hsinchu, TW;

Jack Kuo-Ping Kuo, Pleasanton, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/417 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76814 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 29/41725 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide liner and depositing a metal in the via.


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