The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Dec. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Wei Hsu, Hsinchu County, TW;

Yu-Chung Su, Hsinchu, TW;

Chen-Hao Wu, Hsinchu, TW;

Shen-Nan Lee, Hsinchu County, TW;

Tsung-Ling Tsai, Hsinchu, TW;

Teng-Chun Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/3081 (2013.01); H01L 21/30608 (2013.01); H01L 21/31058 (2013.01); H01L 21/31138 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78 (2013.01);
Abstract

A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.


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