The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Aug. 29, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vivek Yadav, Boise, ID (US);

Fatma Arzum Simsek-Ege, Boise, ID (US);

Sanjeev Sapra, Boise, ID (US);

Thomas A. Figura, Boise, ID (US);

Kangle Li, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 21/67 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); H01L 21/67069 (2013.01); H01L 21/67075 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01); H01L 29/7846 (2013.01);
Abstract

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.


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