The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2021
Filed:
Aug. 27, 2020
Applicant:
Yangtze Memory Technologies Co., Ltd., Hubei, CN;
Inventors:
Zhong Zhang, Hubei, CN;
Yan Ni Li, Hubei, CN;
Assignee:
Yangtze Memory Technologies Co., Ltd., Hubei, CN;
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); G11C 7/18 (2006.01); H01L 27/105 (2006.01); G06F 12/02 (2006.01); H01L 27/11573 (2017.01); H01L 27/11578 (2017.01); H01L 27/24 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); G06F 12/0238 (2013.01); G11C 7/18 (2013.01); G11C 16/04 (2013.01); H01L 27/11573 (2013.01); H01L 27/11578 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01);
Abstract
Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions.