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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11114376 B1

PDFFull Text
Date of Patent:
Sep. 07, 2021

Filed:

Feb. 14, 2020

System for layout design of structure with inter layer vias

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Lin Chuang, Taipei, TW;

Ching-Fang Chen, Taichung, TW;

Jia-Jye Shen, Jhubei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Vuthe Siek

Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.

Find Patent Forward Citations

Chuang, Yi-Lin. (2021). System for layout design of structure with inter layer vias (U.S. Patent No. 11114376). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11114376

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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