The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Apr. 03, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Peter McColgan, Dublin, IE;

Goran H K Bilski, Molndal, SE;

Juan J. Noguera Serra, San Jose, CA (US);

Jan Langer, Chemnitz, DE;

Baris Ozgul, Dublin, IE;

David Clarke, Dublin, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/17 (2006.01); G06F 13/40 (2006.01); H04L 29/08 (2006.01); H04L 12/50 (2006.01); H04L 12/54 (2013.01); H04L 29/06 (2006.01); G06F 15/78 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); H04L 12/56 (2013.01); H04L 29/08351 (2013.01); H04L 63/123 (2013.01); G06F 9/3877 (2013.01); G06F 15/7807 (2013.01); G06F 2213/0038 (2013.01);
Abstract

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.


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